1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and a method for driving the solid-state imaging apparatus.
2. Description of the Related Art
Japanese Patent Laid-Open No. 2007-243324 discloses a column-parallel A/D converter, as a method for improving precision in analog-digital conversion (hereinafter, A/D conversion) of pixel signals. The A/D converter includes a first A/D converter (first processing unit) and a second A/D converter (second processing unit), and the first processing unit performs A/D conversion to generate higher-order bits of digital signals and then the second processing unit performs A/D conversion to generate lower-order bits. The first processing unit performs the first A/D conversion by comparing an analog signal to be converted and a reference voltage. The second processing unit starts charging a capacitor by a constant current source according to the result of the comparison performed by the first processing unit, and ends the charging in response to an edge of a clock signal (a rising edge) supplied immediately thereafter. Then, the second processing unit maintains the voltage for the capacitor and performs the second A/D conversion.
FIG. 9 is a diagram showing states of a reference voltage Vref, an analog signal VA, and an output COMP from a comparator that compares the reference voltage Vref and the analog signal VA, a capacitor voltage VC and a clock signal clk. Here, the charging of the capacitor is performed during a period tc starting from the output COMP being inverted (for example, transition from a lower-state to higher-state) due to inversion in a magnitude relationship between the reference voltage Vref and the analog signal VA ending at the rising edge of the clock signal clk.
However, when the charging of the capacitor is started, the capacitor voltage VC may fluctuate due to noise resulting from switching on/off a switch or the like. Therefore, in the case where the charging period tc is shorter than a time period required for settling the noise, A/D conversion is performed on a voltage value (VC2) fluctuated by the noise, instead of a voltage value (VC1) that should be subjected to the A/D conversion. This may lead to a drop in precision of digital signals.